View ICS844246I_2178816.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

femtoclocks? crystal-to-lvds frequency synthesizer w/integrated fanout buffer ICS844246I idt ? / ics ? lvds frequency synthesizer w/fanout buffer 1 ics844246bgi rev. a november 14, 2007 preliminary g eneral d escription the ICS844246I is a crystal-to-lvds clock synthesizer/fanout buffer designed for fibre channel and gigabit ethernet applications and is a member of the hiperclocks? family of high performance clock solutions from idt. the output frequency can be set using the frequency select pins and a 25mhz crystal for ethernet frequencies, or a 26.5625mhz crystal for a fibre channel. the low phase noise character- istics of the ICS844246I make it an ideal clock for these demanding applications. b lock d iagram p in a ssignment f eatures ? six lvds outputs ? crystal oscillator interface ? output frequency range: 53.125mhz to 333.3333mhz ? crystal input frequency range: 25mhz to 33.333mhz ? rms phase jitter at 125mhz, using a 25mhz crystal (1.875mhz to 20mhz): 0.39ps (typical) ? full 3.3v or 3.3v core, 2.5v output supply mode ? -40c to 85c ambient operating temperature ? available in both standard (rohs 5) and lead-free (rohs 6) packages hiperclocks? ic s q0 v ddo v ddo nq2 q2 nq1 q1 nq0 q0 pll_bypass v dda v dd fb_sel 1 2 3 4 5 6 7 8 9 10 11 12 q3 nq3 q4 nq4 q5 nq5 n_sel1 gnd gnd n_sel0 xtal_out xtal_in osc pll feedback divider output divider 1 0 xtal_in xtal_out pll_bypass nq0 24 23 22 21 20 19 18 17 16 15 14 13 q1 nq1 q2 nq2 q3 nq3 q4 nq4 q5 nq5 fb_sel n_sel1 n_sel0 pullup pulldown pullup pullup ICS844246I 24-lead tssop, e-pad 4.40mm x 7.8mm x 0.90mm body package g package top view s elect f unction t able stupn in oitcnuf les_b f1 les_ n0 les_ ne divid me divid nn /m 000 0 220 1 00 1 0 245 010 0 254 011 0 285 .2 10 0 4 238 10 1 4 246 110 4 264 111 4 22 12 the preliminary information presented herein represents a product in pre-production. the noted characteristics are based on ini tial product characterization and/or qualification. integrated device technology, incorporated (idt) reserves the right to change any circuitry or specificat ions without notice.
idt ? / ics ? lvds frequency synthesizer w/fanout buffer 2 ics844246bgi rev. a november 14, 2007 ICS844246I femtoclocks? crystal-to-lvds frequency synthesizer w/integrated f anout buffer preliminary t able 1. p in d escriptions t able 2. p in c haracteristics l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c n i e c n a t i c a p a c t u p n i 4f p r p u l l u p r o t s i s e r p u l l u p t u p n i 1 5k r n w o d l l u p r o t s i s e r n w o d l l u p t u p n i 1 5k r e b m u ne m a ne p y tn o i t p i r c s e d 2 , 1v o d d r e w o p. s n i p y l p p u s t u p t u o 4 , 32 q , 2 q nt u p t u o. s l e v e l e c a f r e t n i s d v l . r i a p t u p t u o l a i t n e r e f f i d 6 , 51 q , 1 q nt u p t u o. s l e v e l e c a f r e t n i s d v l . r i a p t u p t u o l a i t n e r e f f i d 8 , 70 q , 0 q nt u p t u o. s l e v e l e c a f r e t n i s d v l . r i a p t u p t u o l a i t n e r e f f i d 9s s a p y b _ l l pt u p n ip u l l u p . s r e d i v i d e h t o t t u p n i e h t s a s t u p n i l a t s y r c d n a l l p e h t n e e w t e b s t c e l e s . t u o _ l a t x , n i _ l a t x s t c e l e s , h g i h n e h w . l l p s t c e l e s , w o l n e h w . s l e v e l e c a f r e t n i l t t v l / s o m c v l 0 1v a d d r e w o p. n i p y l p p u s g o l a n a 1 1v d d r e w o p. n i p y l p p u s e r o c 2 1l e s _ b ft u p n in w o d l l u p . s l e v e l e c a f r e t n i l t t v l / s o m c v l . n i p t c e l e s y c n e u q e r f k c a b d e e f , 3 1 4 1 , n i _ l a t x t u o _ l a t x t u p n i . t u p n i e h t s i n i _ l a t x . e c a f r e t n i r o t a l l i c s o l a t s y r c . t u p t u o e h t s i t u o _ l a t x , 5 1 8 1 0 l e s _ n 1 l e s _ n t u p n ip u l l u p. s l e v e l e c a f r e t n i l t t v l / s o m c v l . n i p t c e l e s y c n e u q e r f t u p t u o 7 1 , 6 1d n g. d n u o r g y l p p u s r e w o p 0 2 , 9 15 q , 5 q nt u p t u o. s l e v e l e c a f r e t n i s d v l . r i a p t u p t u o l a i t n e r e f f i d 2 2 , 1 24 q , 4 q nt u p t u o. s l e v e l e c a f r e t n i s d v l . r i a p t u p t u o l a i t n e r e f f i d 4 2 , 3 23 q , 3 q nt u p t u o. s l e v e l e c a f r e t n i s d v l . r i a p t u p t u o l a i t n e r e f f i d : e t o n p u l l u p d n a n w o d l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t r e f e r
idt ? / ics ? lvds frequency synthesizer w/fanout buffer 3 ics844246bgi rev. a november 14, 2007 ICS844246I femtoclocks? crystal-to-lvds frequency synthesizer w/integrated f anout buffer preliminary c rystal f unction t able s t u p n in o i t c n u f ) z h m ( l a t xl e s _ b f1 l e s _ n0 l e s _ nm ) z h m ( o c vn ) z h m ( t u p t u o 5 20000 20 0 520 5 2 5 20010 20 0 545 2 1 5 20100 20 0 550 0 1 5 20110 20 0 58 5 . 2 6 5 21004 20 0 630 0 2 5 21014 20 0 640 5 1 5 21104 20 0 660 0 1 5 21114 20 0 62 10 5 5 2 6 5 . 6 20100 25 2 . 1 3 555 2 . 6 0 1 5 2 6 5 . 6 21004 25 . 7 3 635 . 2 1 2 5 2 6 5 . 6 21014 25 . 7 3 64 5 7 3 . 9 5 1 5 2 6 5 . 6 21104 25 . 7 3 66 5 2 . 6 0 1 5 2 6 5 . 6 21114 25 . 7 3 62 15 2 1 . 3 5 0 30000 20 0 620 0 3 0 30010 20 0 640 5 1 0 30100 20 0 650 2 1 0 30110 20 0 685 7 5 2 . 1 30000 25 2 62 5 . 2 1 3 5 2 . 1 30010 25 2 64 5 2 . 6 5 1 5 2 . 1 30100 25 2 655 2 1 5 2 . 1 30110 25 2 68 5 2 1 . 8 7 3 3 3 3 . 3 30000 27 6 6 6 . 6 6 623 3 3 3 . 3 3 3 3 3 3 3 . 3 30010 27 6 6 6 . 6 6 647 6 6 6 . 6 6 1 3 3 3 3 . 3 30100 27 6 6 6 . 6 6 653 3 3 3 . 3 3 1 3 3 3 3 . 3 30110 27 6 6 6 . 6 6 683 3 3 3 . 3 8
idt ? / ics ? lvds frequency synthesizer w/fanout buffer 4 ics844246bgi rev. a november 14, 2007 ICS844246I femtoclocks? crystal-to-lvds frequency synthesizer w/integrated f anout buffer preliminary t able 4a. p ower s upply dc c haracteristics , v dd = v ddo = 3.3v5%, t a = -40c to 85c t able 4c. lvcmos / lvttl dc c haracteristics , v dd = 3.3v5%, v ddo = 3.3v5% or 2.5v5%, t a = -40c to 85c t able 4b. p ower s upply dc c haracteristics , v dd = 3.3v5%, v ddo = 2.5v5%, t a = -40c to 85c a bsolute m aximum r atings supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, i o contin uous current 10ma surge current 15ma package thermal impedance, ja 24 lead tssop, epad 32.1c/w (0 mps) storage temperature, t stg -65c to 150c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional op- eration of product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability. l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h i e g a t l o v h g i h t u p n i 2v d d 3 . 0 +v v l i e g a t l o v w o l t u p n i 3 . 0 -8 . 0v i h i t n e r r u c h g i h t u p n i l e s _ b fv d d v = n i v 5 6 4 . 3 =0 5 1a , s s a p y b _ l l p 1 l e s _ n , 0 l e s _ n v d d v = n i v 5 6 4 . 3 =5a i l i t n e r r u c w o l t u p n i l e s _ b fv d d v , v 5 6 4 . 3 = n i v 0 =5 -a , s s a p y b _ l l p 1 l e s _ n , 0 l e s _ n v d d v , v 5 6 4 . 3 = n i v 0 =0 5 1 -a l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v d d e g a t l o v y l p p u s e r o c 5 3 1 . 33 . 35 6 4 . 3v v a d d e g a t l o v y l p p u s g o l a n av d d 6 0 . 0 ?3 . 3v d d v v o d d e g a t l o v y l p p u s t u p t u o 5 3 1 . 33 . 35 6 4 . 3v i d d t n e r r u c y l p p u s r e w o p 0 2 1a m i a d d t n e r r u c y l p p u s g o l a n a 6a m i o d d t n e r r u c y l p p u s t u p t u o 5 3 1a m l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v d d e g a t l o v y l p p u s e r o c 5 3 1 . 33 . 35 6 4 . 3v v a d d e g a t l o v y l p p u s g o l a n av d d 6 0 . 0 ?3 . 3v d d v v o d d e g a t l o v y l p p u s t u p t u o 5 7 3 . 25 . 25 2 6 . 2v i d d t n e r r u c y l p p u s r e w o p 0 2 1a m i a d d t n e r r u c y l p p u s g o l a n a 6a m i o d d t n e r r u c y l p p u s t u p t u o 0 2 1a m
idt ? / ics ? lvds frequency synthesizer w/fanout buffer 5 ics844246bgi rev. a november 14, 2007 ICS844246I femtoclocks? crystal-to-lvds frequency synthesizer w/integrated f anout buffer preliminary t able 5. c rystal c haracteristics r e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u n o i t a l l i c s o f o e d o m l a t n e m a d n u f y c n e u q e r f 5 23 3 3 . 3 3z h m ) r s e ( e c n a t s i s e r s e i r e s t n e l a v i u q e 0 5 e c n a t i c a p a c t n u h s 7f p l e v e l e v i r d 1w m . l a t s y r c t n a n o s e r l e l l a r a p f p 8 1 n a g n i s u d e z i r e t c a r a h c : e t o n t able 4d. lvds dc c haracteristics , v dd = v ddo = 3.3v5% t a = -40c to 85c t able 4e. lvds dc c haracteristics , v dd = 3.3v5%, v ddo = 2.5v5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v d o e g a t l o v t u p t u o l a i t n e r e f f i d 9 7 3v m v d o v d o e g n a h c e d u t i n g a m 0 4v m v s o e g a t l o v t e s f f o 4 2 . 1v v s o v s o e g n a h c e d u t i n g a m 0 5v m l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v d o e g a t l o v t u p t u o l a i t n e r e f f i d 7 8 3v m v d o v d o e g n a h c e d u t i n g a m 0 4v m v s o e g a t l o v t e s f f o 9 2 . 1v v s o v s o e g n a h c e d u t i n g a m 0 5v m . n o i t a m r o f n i t u p t u o r o f n o i t a m r o f n i t n e m e r u s a e m r e t e m a r a p o t r e f e r e s a e l p : e t o n
idt ? / ics ? lvds frequency synthesizer w/fanout buffer 6 ics844246bgi rev. a november 14, 2007 ICS844246I femtoclocks? crystal-to-lvds frequency synthesizer w/integrated f anout buffer preliminary t able 6a. ac c haracteristics , v dd = v ddo = 3.3v5%, t a = -40c to 85c t able 6b. ac c haracteristics , v dd = 3.3v5%, v ddo = 2.5v5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f t u o y c n e u q e r f t u p t u o 5 2 1 . 3 53 3 . 3 3 3z h m t ) ? ( t i j) m o d n a r ( r e t t i j e s a h p s m r : e g n a r n o i t a r g e t n i , z h m 5 2 1 z h m 0 2 - z h m 5 7 8 . 1 9 3 . 0s p t ) o ( k s2 , 1 e t o n ; w e k s t u p t u o d b ts p t r t / f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 25 5 3s p c d oe l c y c y t u d t u p t u o 0 5% t k c o l e m i t k c o l l l p 1s m . n o i t c e s n o i t a m r o f n i t n e m e r u s a e m r e t e m a r a p e e s . s n o i t i d n o c d a o l l a u q e h t i w d n a e g a t l o v y l p p u s e m a s e h t t a s t u p t u o n e e w t e b w e k s s a d e n i f e d : 1 e t o n . s t n i o p g n i s s o r c l a i t n e r e f f i d t u p t u o e h t t a d e r u s a e m . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 2 e t o n l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f t u o y c n e u q e r f t u p t u o 5 2 1 . 3 53 3 . 3 3 3z h m t ) ? ( t i j) m o d n a r ( r e t t i j e s a h p s m r : e g n a r n o i t a r g e t n i , z h m 5 2 1 z h m 0 2 - z h m 5 7 8 . 1 8 3 . 0s p t ) o ( k s2 , 1 e t o n ; w e k s t u p t u o d b ts p t r t / f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 20 8 3s p c d oe l c y c y t u d t u p t u o 0 5% t k c o l e m i t k c o l l l p 1s m . n o i t c e s n o i t a m r o f n i t n e m e r u s a e m r e t e m a r a p e e s . s n o i t i d n o c d a o l l a u q e h t i w d n a e g a t l o v y l p p u s e m a s e h t t a s t u p t u o n e e w t e b w e k s s a d e n i f e d : 1 e t o n . s t n i o p g n i s s o r c l a i t n e r e f f i d t u p t u o e h t t a d e r u s a e m . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 2 e t o n
idt ? / ics ? lvds frequency synthesizer w/fanout buffer 7 ics844246bgi rev. a november 14, 2007 ICS844246I femtoclocks? crystal-to-lvds frequency synthesizer w/integrated f anout buffer preliminary t ypical p hase n oise at 125mh z @ 3.3v 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 125mhz rms phase jitter (random) 1.875mhz to 20mhz = 0.39ps o ffset f requency (h z ) n oise p ower dbc hz ? ? ? 1k 10k 100k 1m 10m 100m gb ethernet filter raw phase noise data phase noise result by adding gb ethernet filter to raw data
idt ? / ics ? lvds frequency synthesizer w/fanout buffer 8 ics844246bgi rev. a november 14, 2007 ICS844246I femtoclocks? crystal-to-lvds frequency synthesizer w/integrated f anout buffer preliminary qx nqx float gnd ++ ? power supply scope lvds p arameter m easurement i nformation 3.3v/2.5v o utput l oad ac t est c ircuit o utput r ise /f all t ime clock outputs 20% 80% 80% 20% t r t f v sw i n g t pw t period t pw t period odc = x 100% nq0:nq5 q0:q5 t sk(o) nqx qx nqy qy 3.3v o utput l oad ac t est c ircuit o utput d uty c ycle /p ulse w idth /p eriod o utput s kew out out lvds dc input ? ? ? v os / v os v dd o ffset v oltage s etup d ifferential o utput v oltage s etup ? ? ? 100 out out lvds dc input v od / v od v dd reference document: jedec publication 95, mo-153 v dd scope qx nqx 3.3v5% power supply +? float gnd lvds v dd , v ddo v dda v dda v ddo
idt ? / ics ? lvds frequency synthesizer w/fanout buffer 9 ics844246bgi rev. a november 14, 2007 ICS844246I femtoclocks? crystal-to-lvds frequency synthesizer w/integrated f anout buffer preliminary f igure 1. p ower s upply f iltering 10 v dda 10 f .01 f 3.3v .01 f v dd a pplication i nformation c rystal i nput i nterface the ics844246 has been characterized with 18pf parallel resonant crystals. the capacitor values shown in figure 2 f igure 2. c rystal i npu t i nterface below were determined using an 18pf parallel resonant crystal and were chosen to minimize the ppm error. c1 22p x1 18pf parallel crystal c2 22p xtal_out xtal_in i nputs : lvcmos c ontrol p ins all control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. a 1k resistor can be used. r ecommendations for u nused i nput and o utput p ins o utputs : lvds outputs all unused lvds output pairs can be either left floating or terminated with 100 across. if they are left floating, we recommend that there is no trace attached. p ower s upply f iltering t echniques as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. to achieve optimum jitter perfor- mance, power supply isolation is required. the ICS844246I pro- vides separate power supplies to isolate any high switching noise from the outputs to the internal pll. v dd , v dda , and v ddo should be individually connected to the power supply plane through vias, and 0.01f bypass capacitors should be used for each pin. fig- ure 1 illustrates this for a generic v cc pin and also shows that v dda requires that an additional10 resistor along with a 10f bypass capacitor be connected to the v dda pin.
idt ? / ics ? lvds frequency synthesizer w/fanout buffer 10 ics844246bgi rev. a november 14, 2007 ICS844246I femtoclocks? crystal-to-lvds frequency synthesizer w/integrated f anout buffer preliminary lvcmos to xtal i nterface the xtal_in input can accept a single-ended lvcmos signal through an ac couple capacitor. a general interface diagram is shown in figure 3. the xtal_out pin can be left floating. the input edge rate can be as slow as 10ns. for lvcmos inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. this configuration requires that the output impedance of the driver (ro) plus the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the crystal input will attenuate the signal in half. this can be done in one of two ways. first, r1 and r2 in parallel should equal the transmission line impedance. for most 50 applications, r1 and r2 can be 100 . this can also be accomplished by removing r1 and making r2 50 . f igure 3. g eneral d iagram for lvcmos d river to xtal i nput i nterface xta l _ i n xta l _ o u t vcc r2 ro r1 zo = 50 rs vcc .1uf v dd v dd zo = ro + rs reference document: jedec publication 95, mo-153 3.3v, 2.5v lvds d river t ermination a general lvds interface is shown in figure 4. in a 100 differential transmission line environment, lvds drivers f igure 4. t ypical lvds d river t ermination require a matched load termination of 100 across near the receiver input. 2.5v or 3.3v + - vdd 100 ohm differential transmission line r1 100 lvds_driv er
idt ? / ics ? lvds frequency synthesizer w/fanout buffer 11 ics844246bgi rev. a november 14, 2007 ICS844246I femtoclocks? crystal-to-lvds frequency synthesizer w/integrated f anout buffer preliminary f igure 5. a ssembly for e xposed p ad t hermal r elease p ath ?s ide v iew (d rawing not to s cale ) epad t hermal r elease p ath in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the printed circuit board (pcb) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 5. the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be designed on the pcb between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the pcb to the ground plane(s). the land pattern must be connected to ground through these vias. the vias act as ?heat pipes?. the number of vias (i.e. ?heat pipes?) are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/ slug and the thermal land. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further information, refer to the application note on the surface mount assembly of amkor?s thermally/ electrically enhance leadfame base package, amkor technology. ground plane land pattern solder thermal via exposed heat slug (ground pad) pin pin pad solder pin pin pad solder
idt ? / ics ? lvds frequency synthesizer w/fanout buffer 12 ics844246bgi rev. a november 14, 2007 ICS844246I femtoclocks? crystal-to-lvds frequency synthesizer w/integrated f anout buffer preliminary p ower c onsiderations this section provides information on power dissipation and junction temperature for the ICS844246I. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ICS844246I is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v dd = 3.3v + 5% = 3.465v, which gives worst case results. ? power (core) max = v dd_max * (i dd_max + i dda_max ) = 3.465v * (120ma + 6ma) = 436.59mw ? power (outputs) max = v ddo_max * i ddo_max = 3.465v * 135ma = 467.78mw total power _max = 436.59mw + 467.78mw = 904.37mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks tm devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 32.1c/w per table 7 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.904w * 32.1c/w = 114c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow , and the type of board (single layer or multi-layer). t able 7. t hermal r esistance ja for 24-l ead tssop, e-p ad , f orced c onvection ja by velocity (meters per second) 0 1 2.5 multi-layer pcb, jedec standard test boards 32.1c/w 25.5c/w 24.0c/w
idt ? / ics ? lvds frequency synthesizer w/fanout buffer 13 ics844246bgi rev. a november 14, 2007 ICS844246I femtoclocks? crystal-to-lvds frequency synthesizer w/integrated f anout buffer preliminary r eliability i nformation t ransistor c ount the transistor count for ICS844246I is: 3887 t able 8. ja vs . a ir f low t able for 24 l ead tssop, e-p ad ja by velocity (meters per second) 0 1 2.5 multi-layer pcb, jedec standard test boards 32.1c/w 25.5c/w 24.0c/w
idt ? / ics ? lvds frequency synthesizer w/fanout buffer 14 ics844246bgi rev. a november 14, 2007 ICS844246I femtoclocks? crystal-to-lvds frequency synthesizer w/integrated f anout buffer preliminary p ackage o utline - g s uffix for 24 l ead tssop, e-p ad t able 9. p ackage d imensions l o b m y s s r e t e m i l l i m m u m i n i ml a n i m o nm u m i x a m n4 2 a- -0 1 . 1 1 a5 0 . 05 1 . 0 2 a5 8 . 00 9 . 05 9 . 0 b9 1 . 00 3 . 0 1 b9 1 . 02 2 . 05 2 . 0 c9 0 . 00 2 . 0 1 c9 0 . 07 2 1 . 06 1 . 0 d0 7 . 70 8 . 70 9 . 7 ec i s a b 0 4 . 6 1 e0 3 . 40 4 . 40 5 . 4 ec i s a b 5 6 . 0 l0 5 . 00 6 . 00 7 . 0 p0 . 5 1 p2 . 3 0 8 a a a6 7 0 . 0 b b b0 1 . 0 reference document: jedec publication 95, mo-153
idt ? / ics ? lvds frequency synthesizer w/fanout buffer 15 ics844246bgi rev. a november 14, 2007 ICS844246I femtoclocks? crystal-to-lvds frequency synthesizer w/integrated f anout buffer preliminary while the information presented herein has been checked for both accuracy and reliability, integrated device technology, incorp orated (idt) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or l icenses are implied. this product is intended for use in normal commercial and industrial applications. any other applications such as those requiring high reliability or other extraordinary environmental r equirements are not recommended without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not authorize or warrant any idt product for use in life support devices or critical medical instruments. t able 10. o rdering i nformation r e b m u n r e d r o / t r a pg n i k r a me g a k c a pg n i g a k c a p g n i p p i h se r u t a r e p m e t i g b 6 4 2 4 4 8 s c ii g b 6 4 2 4 4 8 s c id a p - e , p o s s t d a e l 4 2e b u tc 5 8 o t c 0 4 - t i g b 6 4 2 4 4 8 s c ii g b 6 4 2 4 4 8 s c id a p - e , p o s s t d a e l 4 2l e e r & e p a t 0 0 5 2c 5 8 o t c 0 4 - f l i g b 6 4 2 4 4 8 s c il i g b 6 4 2 4 4 8 s c id a p - e , p o s s t " e e r f - d a e l " d a e l 4 2e b u tc 5 8 o t c 0 4 - t f l i g b 6 4 2 4 4 8 s c il i g b 6 4 2 4 4 8 s c id a p - e , p o s s t " e e r f - d a e l " d a e l 4 2l e e r & e p a t 0 0 5 2c 5 8 o t c 0 4 - . t n a i l p m o c s h o r e r a d n a n o i t a r u g i f n o c e e r f - b p e h t e r a r e b m u n t r a p e h t o t x i f f u s " f l " n a h t i w d e r e d r o e r a t a h t s t r a p : e t o n
innovate with idt and accelerate your future networks. contact: www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support netcom@idt.com 480-763-2056 corporate headquarters integrated device t echnology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan integrated device technology singapore (1997) pte. ltd. reg. no. 199707558g 435 orchard road #20-03 wisma atria singapore 238877 +65 6 887 5505 europe idt europe, limited 321 kingston road leatherhead, surrey kt22 7tu england +44 (0) 1372 363 339 fax: +44 (0) 1372 378851 ? 2007 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt, th e idt logo, ics and hiperclocks are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other br ands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa ICS844246I femtoclocks? crystal-to-lvds frequency synthesizer w/integrated f anout buffer preliminary

▲Up To Search▲

Price & Availability of ICS844246I

	To Download ICS844246I Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .